16题答案

根据真值表设计一个全加器，然后用结构的描述方法设计一个6位加法器 library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adder6_vhd is

Port ( x : in STD_LOGIC_VECTOR (5 downto 0); y : in STD_LOGIC_VECTOR (5 downto 0); sum : out STD_LOGIC_VECTOR (5 downto 0); cin : in STD_LOGIC; co : out STD_LOGIC); end adder6_vhd;

architecture Behavioral of adder6_vhd is signal z:std_logic_vector(4 downto 0); component full_adder is port(x,y,cin:in std_logic; sum,co:out std_logic); end component;

begin

u0:full_adder port map(x(0),y(0),cin,sum(0),z(0)); g1:for i in 1 to 4 generate

ux:full_adder port map(x(i),y(i),z(i-1),sum(i),z(i)); end generate;

un:full_adder port map(x(5),y(5),z(4),sum(5),co); end Behavioral; library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full_adder is

Port ( x : in STD_LOGIC; y : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; co : out STD_LOGIC); end full_adder;

architecture Behavioral of full_adder is signal datain:std_logic_vector(2 downto 0); begin

datain<=x&y&cin; sum<=x xor y xor cin; process(datain) begin

case datain is when\"000\"=>co<='0'; when\"001\"=>co<='0'; when\"010\"=>co<='0'; when\"011\"=>co<='1'; when\"100\"=>co<='0'; when\"101\"=>co<='1'; when\"110\"=>co<='1'; when\"111\"=>co<='1'; when others=>co<='0'; end case; end process; end Behavioral;